1. Field of the Invention
The present invention is related to semiconductor integrated circuit devices, and, in particular, to a semiconductor integrated circuit device that includes a test element group circuit.
2. Discussion of Related Art
In general, a plurality of integrated circuit chips are formed on a pure semiconductor substrate, so-called a wafer, by performing well-known semiconductor processes, each of which has its specific property. After fabrication processes are completed, the wafer is broken up into individual integrated circuit chips. An empty space is provided between integrated circuit chips to separate adjacent integrated circuit chips, and such an empty space is called a scribe line region or a scribe lane region. Elements of an integrated circuit chip are not formed on this scribe line region.
To check the electrical properties of various elements of an integrated circuit chip, a pattern of measuring elements or test elements is formed on a scribe line region of the semiconductor wafer. The pattern of measuring elements or test elements is called a test element group circuit. The test element group circuit is electrically tested to determine whether elements in an integrated circuit chip are properly formed. Semiconductor devices including measuring or test elements are disclosed in U.S. Pat. No. 6,177,733 entitled “SEMICONDUCTOR DEVICE,” U.S. Pat. No. 5,949,090 entitled “MOS TEG STRUCTURE,” and U.S. Pat. No. 5,654,582 entitled “CIRCUIT WAFER AND TEG PAD ELECTRODE.”
A test element group circuit is formed using the same processes as those for forming elements in an integrated circuit chip. Therefore, electrical properties of the test element group circuit are the same as that of elements in the integrated circuit chip. And, electrical properties of the elements of the IC chip can be measured by measuring that element group circuit. However, as the number of dies per wafer is increasingly reduced, it is considerably hard to exactly analyze properties of integrated circuit chips through testing of the test element group circuit. For this reason, a method of analyzing properties of integrated circuit chips has been developed by forming a test element group circuit in an integrated circuit chip, instead of forming it at a scribe line region.
One example of a test element group circuit formed in a chip is disclosed in Japanese Patent Laid-open No. 05-021554 entitled “SEMICONDUCTOR INTEGRATED CIRCUIT” filed on Nov. 7, 1991. The patent describes a technique that prevents defective products from being delivered to consumers by measuring AC properties via an inverter chain formed in a chip.
An integrated circuit device that includes a test element group circuit for measuring AC properties is illustrated in FIG. 1. Referring to FIG. 1, a semiconductor integrated circuit device 1 has a test element group circuit 14 that is connected between pads 10 and 12. The test element group circuit 14 includes a plurality of inverters 16–22 connected in series between the pads 10 and 12.
In operation, probe pins or needles are connected to the pads 10 and 12 in a wafer-level test mode, respectively. A signal applied to the pad 10 is outputted to the pad 12 via the test element group circuit 14. AC properties of the test element group circuit 14 are analyzed by parsing the signal outputted from the pad 12.
FIG. 2 is a top view of a test element group circuit shown in FIG. 1. Referring to FIG. 2, a reference numeral 30 indicates an N-well region formed in a semiconductor substrate (not shown), and a reference numeral 32 indicates an active region defined by device isolation. A reference numeral 34 indicates a polysilicon gate. In FIG. 2, a PMOS transistor of the respective inverters 16–22 is formed on the N-well region 30, and an NMOS transistor of the respective inverters 16–22 is formed on the semiconductor substrate.
Device isolation 38 provides an isolation layer.
FIG. 3 is a cross-sectional view of a test element group circuit taken along a dotted line A–A′ of FIG. 2. Referring to FIG. 3, a drain 36 of a PMOS transistor of an inverter 16 is connected via a contact structure 40 to an interconnection M0, which is electrically connected to a gate 34 of a PMOS transistor of an inverter 18 via a contact structure 42. The interconnection may be formed of one of tungsten and polysilicon. Although not shown in figures, a drain of an NMOS transistor of the inverter 16 may be connected to a gate of an NMOS transistor of the inverter 18, by the same manner as illustrated in FIG. 3. It is to be understood that the remaining inverters are connected by the same manner as described above. Here, the contact structures 40 and 42 are called local interconnections, respectively.
As shown in FIGS. 1–3, the inverters 16–22 that form a test element group circuit 14 for measuring AC properties are connected to each other via corresponding interconnections (or, signal paths each formed to have contact structures 40 and 42 and an interconnection M0), which are formed with tungsten or polysilicon. In the case of the test element group circuit 14 having such a signal path structure, AC properties are tested by considering electric properties of MOS transistors such as drain current, threshold voltage, and so forth.